1. Field of the Invention
The present invention relates to a video signal reproducing apparatus, and more particularly, to a video signal reproducing apparatus and method, including an apparatus and method for adjusting a horizontal synchronous signal.
2. Description of the Related Art
FIG. 1 is a schematic block diagram of a conventional video signal reproducing apparatus. The conventional video signal reproducing apparatus includes an analog-to-digital converter (ADC) 100, a phase locked loop (PLL) circuit 110, a line buffer 120, a timing control logic 130, and a scaler 140.
The ADC 100 converts an input analog video signal into a digital video signal.
The PLL circuit 110 receives an input horizontal synchronous signal H_sync, and produces a video clock Video_Clock and a clock signal DCLK.
The line buffer 120 stores a display line of a digital video signal (RGB signal) in a unit of a display line. The line buffer 120 has a smaller memory capacity than a frame buffer, which can accommodate all the data displayed on a screen.
The timing control logic 130 controls writing to and reading from the line buffer 120, stores an output resolution, and outputs the video clock Video_Clock_out, a horizontal synchronous signal H_sync_out, and a vertical synchronous signal V-sync_out, for reproducing video.
The scaler 140 converts the digital video signal stored in the line buffer 120, into a video signal with a resolution suitable for reproduction and then outputs the video signal having the converted resolution.
In the video signal reproducing apparatus shown in FIG. 1, the input video signal is temporarily stored in the line buffer 120 so a calculation operation can be performed to convert the input video signal into a video signal having a resolution suitable for a display device and allow for buffering of data due to the different speeds of inputting and outputting the video signal. The input speed of the input video signal and the recording speed of the input video signal in the line buffer 120 are set by a user, but may vary according to the condition of the source used for reproducing the input video signal. However, the video signal output from the video signal reproducing apparatus has a fixed period depending on the characteristics of the display device. Thus, as writing and reading operations in the line buffer 120 are repeated, the timing of writing data to the line buffer 120 may outpace the timing of reading data from the line buffer 120.
In order to solve this problem, various control signals input to the line buffer 120 are reset right after the output vertical synchronous signal V_sync_out is generated to keep a predetermined timing between the write operation and the read operation in the line buffer 120, i.e., input and output timing periods of the video signal.
However, such a reset based on the output vertical synchronous signal may affect a period of the output horizontal synchronous signal H_sync_out. There are as many output horizontal synchronous signals as horizontal lines of a frame in a period of the output vertical synchronous signal. If resetting is performed immediately after the output vertical synchronous signal is generated, the point in time when the output horizontal synchronous signal is generated may be, at maximum, two periods slower than the point in time when the previous output horizontal synchronous signal was generated. FIG. 2 illustrates an output horizontal synchronous signal, which is delayed according to a reset signal being applied immediately after an output vertical synchronous signal is produced.
In addition, when a period of an output horizontal synchronous signal falls outside an allowed period of a horizontal synchronous signal required by the display device, an undesirable phenomenon such as bouncing, rolling, or the like may occur during display of the video signal.